1. Field of the Invention
The embodiments of the disclosure relates generally to design of integrated circuits (IC), and more specifically to producing ICs which are less susceptible to degradations caused due to operational stress.
2. Related Art
Operational stress (or succinctly “stress”) is caused by applying voltage/current to various circuit elements such as transistors, interconnects, capacitors, etc., within an IC as is well known in the relevant arts. The operational stress on a circuit element is generally a function of the strength of the voltage/current (applied to the element), operating temperature (in which the element operates) and duration of operation (usually of magnitude of months or years) of the circuit element, though other variables such as radiation and operational altitude type of attributes may also be considered depending on the environment of interest.
Operational stress degrades circuit elements. Degradation (stress degradation) refers to change in a fundamental characteristic/composition of the circuit element due to the application of stress. In case of transistors, degradation is caused due to a phenomenon commonly referred to as Negative Bias Temperature Instability (NBTI) in case of PMOS transistors, and due to as Channel Hot Carrier (CHC) in case of NMOS transistors. In case of metal interconnects, the degradation is caused due to electromigration or Joule heating phenomenon. However, other phenomenon causes stress in other elements due to the element type and/or material used for fabrication of the element, as would be apparent to a skilled practitioner.
Different elements of ICs may respond differently to the applied stress. For illustration, Vt (threshold voltage at which the transistor changes state from 1 to 0 or vice versa), an example parameter representing stress degradation in case of transistors, changes due to stress. The changes in Vt in turn changes (typically increases) the switching time (and thus the delay) of the transistor, thereby potentially causing the IC to deviate from the desired operation (typically by malfunctioning) over a period of time. Similarly, in case of metal interconnects, the stress due to electromigration or Joule heating changes the resistance thereby affecting the delay of the circuit. Based on the nature of the stress, the change in the delay could be a gradual degradation or a catastrophic failure.
It is accordingly desirable that ICs be designed to be less susceptible to such stress degradations.